Computer Architecture · FPGA / RTL · Hardware Acceleration · PQC

Shahriar Rizvi

Seeking PhD opportunities in the USA · Fall 2027

I build and evaluate computing systems close to the hardware: FPGA accelerators, RTL architectures, and hardware–software co-design. My research interests include computer architecture, reconfigurable computing, and efficient hardware implementations of post-quantum cryptography (PQC).

B.Sc. Engg. in Computer Science & Engineering from RUET with a final CGPA of 3.89/4.00 and ranked 5th among 181 students in the CSE Department.

Chicago, Illinois, USA U.S. permanent resident

View CV ↗ View Research Contact

01 — About

Engineering systems from architecture to hardware.

A research-oriented CSE graduate with hands-on work spanning RTL, FPGA prototypes, hardware acceleration, computing systems, and mentoring.

I am a Computer Science & Engineering graduate from Rajshahi University of Engineering & Technology (RUET). I completed an Outcome-Based Education (OBE) curriculum with a final CGPA of 3.89/4.00, ranking 5th among 181 students in the CSE Department.

My research centers on computer architecture, FPGA/RTL systems, hardware acceleration, reconfigurable computing, and hardware–software co-design. My peer-reviewed work also extends into multimodal deepfake detection, digital provenance, and WiFi–visible-light indoor positioning.

I am also actively studying post-quantum cryptography (PQC), with particular interest in efficient FPGA/RTL implementations, hardware acceleration, and hardware–software co-design for PQC algorithms. I hope to develop this interest further through doctoral research.

I enjoy building systems close to the hardware—from SystemVerilog datapaths and finite-state machines to FPGA prototyping, bare-metal execution, and operating-system development—while keeping experimental results reproducible and explainable.

LocationChicago, Illinois, USA

ResidencyU.S. permanent resident

Seeking PhD opportunitiesFall 2027 admission · USA

EducationB.Sc. Engg. in CSE, RUET · 2026

Research interestsComputer Architecture · FPGA/RTL · Hardware Acceleration · VLSI · Post-Quantum Cryptography (PQC)

TeachingProgramming, algorithms, digital systems, architecture, OS, networks, AI/ML

02 — Research

FPGA systems, from design to evaluation.

My primary direction is computer architecture and hardware acceleration. The thesis below brings together fixed-point RTL, FPGA prototyping, and reproducible validation; selected publications follow.

Undergraduate Thesis · Completed 2026

QFlow: A Fixed-Point FPGA Accelerator for Adaptive Key-Resource-Aware Route-Candidate Evaluation in Trusted-Relay QKD Networks

Supervised by Prof. Dr. Md. Nazrul Islam Mondal, Department of CSE, RUET. The work proposes a fixed-point FPGA accelerator for adaptive, key-resource-aware route-candidate evaluation, combining hardware-efficient route scoring with adaptive profile selection. The RTL architecture was prototyped on a Digilent Nexys 3 (Spartan-6 XC6LX16), with an offline reinforcement-learning policy mapped into deterministic hardware policy/profile ROMs.

0 mismatchesAcross 420 validation records / 3,780 comparisons

≈ 102.02 MHzPost-route frequency

2.048 μsMean kernel latency

Explore thesis source files ↗

Selected publications

[1] Published · IEEE ICECTE 2026

FPGA Acceleration of Quantum Circuit Primitives: Fixed-Point Microcoded Design and CPU Comparison

Shahriar Rizvi and Md. Nazrul Islam Mondal

IEEE ICECTE 2026 · DOI: 10.1109/ICECTE69292.2026.11429464

View DOI ↗

[2] Published · IEEE ICCIT 2025

Beyond Artifacts: Semantic Deepfake Detection and Digital Provenance Tracking with Multimodal Large Language Models

Jabunnesa Jahan Sara, Shahriar Rizvi, and Tasfia Jannat Tasfi

IEEE ICCIT 2025 · DOI: 10.1109/ICCIT68739.2025.11490141

View DOI ↗

[3] IEEE SPICSCON 2026 · Accepted, to appear

Topology-Aware Adaptive WiFi–Visible-Light Fusion for Robust Simulated Indoor Positioning

Shahriar Rizvi, Tasfia Jannat Tasfi, and Md. Nazrul Islam Mondal

IEEE SPICSCON 2026 · Accepted, to appear.

Research profile

Research interests for doctoral study

I am interested in how architecture, numerical precision, and hardware–software partitioning affect accelerator latency and resource use. I also want to explore efficient FPGA/RTL implementations and hardware acceleration of post-quantum cryptography (PQC). I hope to investigate these directions through RTL design, FPGA experiments, and reproducible systems evaluation.

Google Scholar ↗

03 — Projects

Selected technical projects.

Projects chosen to show depth in processor design, systems, computer graphics, and applied computer vision.

Ongoing · RTL / Computer Architecture

SigmaCore RISC-V CPU Design

Implementing a 32-bit multicycle RISC-V CPU in SystemVerilog with modular ALU, control unit, register file, memory, instruction decoder, sign extender, and top-level testbench. FSM-based control is verified with Icarus Verilog simulation and GTKWave tracing.

SystemVerilogRISC-VFSMIcarus VerilogGTKWave

View project ↗

Ongoing · Operating Systems

SigmaCore Operating System

Developing a small operating system from scratch with assembly-focused boot and low-level components, connecting processor architecture, bare-metal execution, and core operating-system concepts.

Operating SystemsAssemblyBare-metalComputer Architecture

View project ↗

Completed · Computer Graphics

Bezier Breakout: Curve Ball Arena

Created a C++17 OpenGL/GLUT game with procedural graphics and primitives, including paddle control, levels, camera/help controls, and no external game engine.

C++17OpenGLGLUTProcedural Graphics

View project ↗

Completed · AI / Computer Vision

AI-Powered Attendance System

Implemented a Python facial-recognition attendance system with GUI, model training, real-time recognition, CSV import/export, and attendance reporting.

PythonComputer VisionFace RecognitionGUI

View project ↗

04 — Education

Academic background.

Strong performance across undergraduate engineering and earlier science education.

B.Sc. Engg. in Computer Science & Engineering

Rajshahi University of Engineering & Technology (RUET), Bangladesh

Completed 2026 · Outcome-Based Education (OBE) curriculum · Graduated 5th among 181 students in the CSE Department

The CSE program is accredited by BAETE for 31 January 2026–30 January 2032, with Washington Accord recognition from 31 January 2026. View official accreditation register ↗

3.89 / 4.00CGPA

Higher Secondary Certificate (HSC), Science

Government Edward College, Pabna, Bangladesh

2020

5.00 / 5.00GPA

Secondary School Certificate (SSC), Science

Pabna Zilla School, Pabna, Bangladesh

2018

5.00 / 5.00GPA

05 — Recognition

Honours & awards.

Selected distinctions spanning RTL/VLSI, quantum computing, scholarships, entrepreneurship, programming, mathematics, and science.

Champion — VLSITHON 2.0 (2024)

RTL Design category · ULKASEMI.

Team: RUET Digital Dynamos

Read coverage in The Daily Star ↗

RUET Digital Dynamos receiving the RTL champion award at the VLSITHON 2.0 prize-giving ceremony — Team award presentation · View full size ↗

VLSITHON 2.0 champion trophy, certificate, and RUET Digital Dynamos prize cheque — Trophy and certificate · View full size ↗

1st Prize & Funding Recipient

University Innovation Hub Program (UIHP) · 2025.

UIHP team holding the BDT 50,000 prize and funding cheque — UIHP prize and funding presentation · 2025 · View full size ↗

Bronze Honour — IYMC

International Youth Math Challenge · 2024 final round.

IYMC Bronze Honour certificate awarded to Shahriar Rizvi for the 2024 final round, issued 26 February 2025 — 2024 final round · Certificate issued February 2025 · View full size ↗

Graduated 5th among 181 CSE Students

B.Sc. Engg. final result, RUET · 2026.

Quantum Excellence

IBM Qiskit Global Summer School · 2025.

Verify credential on Credly ↗

Government Technical Scholarship

Recipient for all four undergraduate years.

Champion — HULT Prize on Campus RUET

2023.

Earlier Academic Distinctions

National High School Programming Contest Champion (2016); Science Olympiad Champion (2018, 2019); Creative Talent Hunt Regional Champion (2019); Bangladesh Math Olympiad regional 1st runner-up awards (2017, 2019); Science Fair 1st runner-up (2020).

06 — Teaching & Leadership

Mentoring, instruction & service.

Teaching experience is paired with sustained academic and technical leadership.

Competitive Programming Instructor / Mentor

RUET Analytical and Programming Lab (RAPL) · 1+ years

Mentored 100+ junior students in C/C++, algorithms, debugging, contest-oriented problem solving, and peer-learning sessions.

Private Tutor / Academic Mentor

5+ years

Long-term mentoring for SSC, HSC, engineering admission, and selected university-level subjects with a concept-first, step-by-step approach.

Class Representative & Coordinator

Department of CSE, RUET · 2023–2025

Coordinated academic communication among faculty members and students, including schedules, course updates, notices, and departmental matters.

Campus Ambassador

ULKASEMI Private Ltd. · 2025–2026

Promoted semiconductor, RTL, and VLSI career awareness through campus-level student engagement.

Official Ambassador

International Computer Science Competition (ICSC) · 2025

Promoted participation in international computer science, algorithmic, and problem-solving competitions.

Vice President

RUET Computing Society · 2025–2026

Contributed to peer learning, computing activities, student engagement, and technical-event coordination.

Joint Secretary

Pabna District Association, RUET · 2025–2026

Supported student networking, event organization, and community coordination.

07 — Skills

Technical toolkit.

Tools I use across RTL design, systems programming, simulation, and experimental evaluation.

Programming

C, C++, Python, SQL, JavaScript/Node.js, LaTeX

HDL / Hardware

Verilog, SystemVerilog, RTL Design, FPGA Prototyping, Fixed-Point Design, FSM Design, CPU Datapath & Control

Systems / Architecture

Computer Architecture, Assembly, Bare-Metal Programming, Operating-System Development / Concepts, OpenGL/GLUT

EDA / Development

Vivado, Icarus Verilog, Verilator, GTKWave, Git, GitHub, Linux/Ubuntu, Jupyter/Colab

AI / Data

Classification, Feature Engineering, Model Evaluation, Explainable AI, Computer Vision

Web / Databases

Django, Laravel, SQL Database Design, SQLite, MySQL

Networking / Sensing

IP Addressing, Subnetting, VLANs, RIP/OSPF, Cisco Packet Tracer, Wi-Fi Sensing, Visible-Light Positioning

Research & Academic Interests

Computer ArchitectureFPGA/RTL SystemsHardware AccelerationPost-Quantum Cryptography (PQC)Reconfigurable Computing Hardware–Software Co-DesignOperating SystemsEmbedded SystemsQuantum Computing Systems Artificial IntelligenceComputer NetworksWi-Fi / Visible-Light PositioningComputer Graphics

08 — Contact

Let’s discuss Fall 2027 PhD research.

I am seeking Fall 2027 PhD opportunities at U.S. universities in computer architecture, FPGA/RTL systems, hardware acceleration, post-quantum cryptography (PQC), and hardware–software co-design. If these interests align with your group, I would welcome a conversation about research fit and potential openings.

Chicago, Illinois, USA · U.S. permanent resident
shahriar10rizvi@gmail.com

Discuss research fit View CV ↗ LinkedIn