[1] IEEE ICECTE 2026
FPGA Acceleration of Quantum Circuit Primitives: Fixed-Point Microcoded Design and CPU Comparison
IEEE ICECTE 2026 · DOI: 10.1109/ICECTE69292.2026.11429464
View DOI ↗CSE Graduate · Computer Architecture · FPGA / RTL · VLSI Research
Shahriar Rizvi
Computing-systems researcher and engineer focused on computer architecture, FPGA/RTL systems, hardware acceleration, and hardware–software co-design.
B.Sc. Engg. in Computer Science & Engineering from RUET with a final CGPA of 3.89/4.00 and 5th rank out of 181 students in the CSE Department.
01 — About
Engineering systems from architecture to hardware.
A research-oriented CSE graduate with hands-on work spanning RTL, FPGA prototypes, hardware acceleration, computing systems, and mentoring.
I am a Computer Science & Engineering graduate from Rajshahi University of Engineering & Technology (RUET). I completed an Outcome-Based Education (OBE) curriculum with a final CGPA of 3.89/4.00, ranking 5th among 181 students in the CSE Department.
My research centers on computer architecture, FPGA/RTL systems, hardware acceleration, reconfigurable computing, and hardware–software co-design. My peer-reviewed work also extends into multimodal deepfake detection, digital provenance, and WiFi–visible-light indoor positioning.
I enjoy building systems close to the hardware—from SystemVerilog datapaths and finite-state machines to FPGA prototyping, bare-metal execution, and operating-system development—while keeping experimental results reproducible and explainable.
LocationRajshahi / Dhaka, Bangladesh
EducationB.Sc. Engg. in CSE, RUET · 2026
Research identityComputer Architecture · FPGA/RTL · Hardware Acceleration · VLSI
TeachingProgramming, algorithms, digital systems, architecture, OS, networks, AI/ML
02 — Education
Academic background.
Strong performance across undergraduate engineering and earlier science education.
B.Sc. Engg. in Computer Science & Engineering
Rajshahi University of Engineering & Technology (RUET), Bangladesh
3.89 / 4.00CGPA
Higher Secondary Certificate (HSC), Science
Government Edward College, Pabna, Bangladesh
5.00 / 5.00GPA
Secondary School Certificate (SSC), Science
Pabna Zilla School, Pabna, Bangladesh
5.00 / 5.00GPA
03 — Research
Research publications & undergraduate thesis.
Work across FPGA acceleration, multimodal AI, digital provenance, and hybrid indoor positioning.
[2] IEEE ICCIT 2025
Beyond Artifacts: Semantic Deepfake Detection and Digital Provenance Tracking with Multimodal Large Language Models
IEEE ICCIT 2025 · DOI: 10.1109/ICCIT68739.2025.11490141
View DOI ↗[3] IEEE SPICSCON 2026 · Accepted, to appear
Topology-Aware Adaptive WiFi–Visible-Light Fusion for Robust Simulated Indoor Positioning
IEEE SPICSCON 2026 · Accepted, to appear.
Research profile
Primary research direction
Google Scholar ↗Undergraduate Thesis · Completed 2026
QFlow: A Fixed-Point FPGA Accelerator for Adaptive Key-Resource-Aware Route-Candidate Evaluation in Trusted-Relay QKD Networks
Supervised by Prof. Dr. Md. Nazrul Islam Mondal, Department of CSE, RUET. The work proposes a fixed-point FPGA accelerator for adaptive, key-resource-aware route-candidate evaluation, combining hardware-efficient route scoring with adaptive profile selection. The RTL architecture was prototyped on a Digilent Nexys 3 (Spartan-6 XC6LX16), with an offline reinforcement-learning policy mapped into deterministic hardware policy/profile ROMs.
0 mismatchesAcross 420 validation records / 3,780 comparisons
≈ 102.02 MHzPost-route frequency
2.048 μsMean kernel latency
04 — Projects
Selected technical projects.
Projects chosen to show depth in processor design, systems, computer graphics, and applied computer vision.
Ongoing · RTL / Computer Architecture
SigmaCore RISC-V CPU Design
Implementing a 32-bit multicycle RISC-V CPU in SystemVerilog with modular ALU, control unit, register file, memory, instruction decoder, sign extender, and top-level testbench. FSM-based control is verified with Icarus Verilog simulation and GTKWave tracing.
SystemVerilogRISC-VFSMIcarus VerilogGTKWave
View project ↗
Ongoing · Operating Systems
SigmaCore Operating System
Developing a small operating system from scratch with assembly-focused boot and low-level components, connecting processor architecture, bare-metal execution, and core operating-system concepts.
Operating SystemsAssemblyBare-metalComputer Architecture
View project ↗
Completed · Computer Graphics
Bezier Breakout: Curve Ball Arena
Created a C++17 OpenGL/GLUT game with procedural graphics and primitives, including paddle control, levels, camera/help controls, and no external game engine.
C++17OpenGLGLUTProcedural Graphics
View project ↗
Completed · AI / Computer Vision
AI-Powered Attendance System
Implemented a Python facial-recognition attendance system with GUI, model training, real-time recognition, CSV import/export, and attendance reporting.
PythonComputer VisionFace RecognitionGUI
View project ↗
05 — Recognition
Honours & awards.
Selected distinctions spanning RTL/VLSI, quantum computing, scholarships, entrepreneurship, programming, mathematics, and science.
5th Rank — CSE Department
B.Sc. Engg. final result, RUET · 2026.
Champion — VLSITHON 2024
RTL Section · ULKASEMI.
Quantum Excellence
IBM Qiskit Global Summer School · 2025.
Government Technical Scholarship
Recipient for all four undergraduate years.
1st Prize & Funding Recipient
University Innovation Hub Program (UIHP) · 2025.
Champion — HULT Prize on Campus RUET
2023.
Bronze Honour — IYMC
International Youth Math Challenge · 2024.
Earlier Academic Distinctions
National High School Programming Contest Champion (2016); Science Olympiad Champion (2018, 2019); Creative Talent Hunt Regional Champion (2019); Bangladesh Math Olympiad regional 1st runner-up awards (2017, 2019); Science Fair 1st runner-up (2020).
06 — Teaching & Leadership
Mentoring, instruction & service.
Teaching experience is paired with sustained academic and technical leadership.
Competitive Programming Instructor / Mentor
Mentored 100+ junior students in C/C++, algorithms, debugging, contest-oriented problem solving, and peer-learning sessions.
Private Tutor / Academic Mentor
Long-term mentoring for SSC, HSC, engineering admission, and selected university-level subjects with a concept-first, step-by-step approach.
Class Representative & Coordinator
Coordinated academic communication among faculty members and students, including schedules, course updates, notices, and departmental matters.
Campus Ambassador
Promoted semiconductor, RTL, and VLSI career awareness through campus-level student engagement.
Official Ambassador
Promoted participation in international computer science, algorithmic, and problem-solving competitions.
Vice President
Contributed to peer learning, computing activities, student engagement, and technical-event coordination.
Joint Secretary
Supported student networking, event organization, and community coordination.
07 — Skills
Technical toolkit.
Presented as domains rather than subjective percentage bars.
Programming
C, C++, Python, SQL, JavaScript/Node.js, LaTeX
HDL / Hardware
Verilog, SystemVerilog, RTL Design, FPGA Prototyping, Fixed-Point Design, FSM Design, CPU Datapath & Control
Systems / Architecture
Computer Architecture, Assembly, Bare-Metal Programming, Operating-System Development / Concepts, OpenGL/GLUT
EDA / Development
Vivado, Icarus Verilog, Verilator, GTKWave, Git, GitHub, Linux/Ubuntu, Jupyter/Colab
AI / Data
Classification, Feature Engineering, Model Evaluation, Explainable AI, Computer Vision
Web / Databases
Django, Laravel, SQL Database Design, SQLite, MySQL
Networking / Sensing
IP Addressing, Subnetting, VLANs, RIP/OSPF, Cisco Packet Tracer, Wi-Fi Sensing, Visible-Light Positioning
Research & Academic Interests
Computer ArchitectureFPGA/RTL SystemsHardware AccelerationReconfigurable Computing
Hardware–Software Co-DesignOperating SystemsEmbedded SystemsQuantum Computing Systems
Artificial IntelligenceComputer NetworksWi-Fi / Visible-Light PositioningComputer Graphics