// Hardware Engineer · VLSI · Quantum Computing

Shahriar
Rizvi

Final-year CSE student at RUET, Bangladesh. Champion at VLSITHON 2024, IBM Qiskit Excellence awardee. Passionate about building hardware from the ground up — from RTL to GDSII.

3.90
CGPA / 4.00
10+
Awards Won
4+
Projects
2026
Graduating
VerilogSystemVerilog RISC-VRTL Design QiskitFPGA Network Eng.C / C++
currently_building.sh
$project = "SigmaCore RISC-V CPU"
$stack   = "SystemVerilog → GDSII"
$status  = ⬤ active
01 — About

Building Hardware
from First Principles

I am Shahriar Rizvi, a final-year Computer Science & Engineering student at Rajshahi University of Engineering & Technology (RUET), Bangladesh, maintaining a CGPA of 3.90/4.00. My passion lies at the intersection of hardware and computing — designing processors from scratch, exploring quantum algorithms, and building robust network architectures.

My work spans RTL design using Verilog and SystemVerilog, where I am currently designing a full RISC-V CPU from RTL all the way to GDSII tape-out. I am simultaneously developing an AI-powered attendance system and have a strong track record in competitive programming and mathematical olympiads.

I earned the IBM Qiskit Excellence badge at the Qiskit Global Summer School 2025, and was Champion at VLSITHON 2024 in the RTL Section. I serve as Campus Ambassador for ULKASEMI Private LTD and ICSC, bridging academia and industry. In 2025, my startup received first prize and funding from the University Innovation Hub Program (UIHP).

Currently exploring opportunities for graduate study (MS/PhD) in VLSI, quantum computing, and computer architecture at leading US universities for Fall 2026–2027.

Quick Info

Rajshahi, Bangladesh
shahriar10rizvi@gmail.com
RUET, CSE Dept.
Age 22 · Graduating 2026

Research Interests

VLSI & RTL Design
Quantum Computing
Network Engineering
Competitive Programming
02 — Education

Academic Background

B.Sc. in Computer Science & Engineering
Rajshahi University of Engineering & Technology (RUET), Bangladesh
2021 – 2026 (Expected)
3.90
CGPA / 4.00
Higher Secondary Certificate (H.S.C.)
Government Edward College, Pabna, Bangladesh
2020
5.00
GPA / 5.00
Secondary School Certificate (S.S.C.)
Pabna Zilla School, Pabna, Bangladesh
2018
5.00
GPA / 5.00
03 — Projects

Selected Work

In Progress

SigmaCore — RISC-V CPU

Designing a full RISC-V architecture processor from scratch using SystemVerilog — Memory, ALU, and Control Unit at RTL level, targeting GDSII tape-out. Future plans include a custom OS and compiler on the silicon.

SystemVerilogRISC-VRTLGDSII
View on GitHub
In Progress

CPU Design 01

Designing a CPU from scratch in Verilog — implementing Memory, ALU, and Control Unit at RTL level. A deep foundational study in digital computer architecture and HDL engineering.

VerilogRTL DesignALUControl Unit
View on GitHub
Complete

AI Powered Attendance System

An automated attendance management system using face recognition that updates attendance sheets in real-time without manual intervention.

PythonFace RecognitionAI/MLOpenCV
View on GitHub
Complete

BoiKothon — Book Review Platform

A full-stack web platform for sharing and discovering book reviews. Built with Django for the backend and HTML/PHP for the frontend.

DjangoPythonHTMLPHP
View on GitHub
04 — Achievements

Honours & Recognition

🏆
Champion — VLSITHON RTL Section
ULKASEMI Private LTD · 2024
⚛️
Quantum Excellence — Qiskit Global Summer School
IBM · 2025
🥉
Bronze Honour — International Youth Math Challenge
IYMC · 2024
💡
1st Prize — University Innovation Hub Program (UIHP)
Startup Funded · 2025
🏆
Champion — HULT Prize On Campus
RUET · 2023
💻
Champion — National High School Programming Contest
2016
📐
1st & 2nd Runners Up — Bangladesh Math Olympiad Regional
2017 & 2019
🔬
Champion — Science Olympiad
2018 & 2019
🎯
Champion — Creative Talent Hunt Regional
2019
🥈
1st Runners Up — Science Fair
2020
05 — Skills

Technical Expertise

Hardware Design
RTL / HDL
Verilog
SystemVerilog
RTL Design
FPGA / Embedded
Programming
Languages
C / C++
Python
SQL / Node.js
LaTeX
Quantum & Networks
Emerging Tech
Qiskit
Routing (RIP/OSPF)
Subnetting / VLSM
Cisco Packet Tracer
06 — Experience & Roles

Positions of Responsibility

June 2025 – Present
Official Ambassador — ICSC
International Computer Science Competition
Representing ICSC at RUET, coordinating student participation in international programming competitions.
March 2025 – Present
Campus Ambassador — ULKASEMI
ULKASEMI Private LTD
Bridging academia and industry by connecting students with VLSI-focused opportunities and competitions organized by ULKASEMI.
2021 – Present
Class Representative & Coordinator
RUET CSE-2020 Batch
Managing departmental schedules and events, acting as liaison between students and faculty, cultivating leadership and organizational skills.
2021 – Present
Vice President — RUET Computing Society
RUET
Leading computing society initiatives, organizing technical workshops and hackathons, mentoring junior students in competitive programming.
2021 – Present
Joint Secretary — Pabna District Association RUET
RUET
Managing association affairs and connecting students from Pabna district studying at RUET.
07 — Blog & Writing

Thoughts & Articles

Beyond engineering, I write about technology, quantum computing, hardware design, and ideas that shape the future. Occasional reflections on learning and research.

08 — Contact

Let's Connect

I'm open to research collaborations, academic discussions, graduate school inquiries, and professional opportunities in VLSI, quantum computing, and hardware engineering.

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